As far as I know, clock speed is still pretty nice to have, but chip development has shifted towards adding multiple cores because it basically became technologically impossible to continue increasing clock speeds.
A nice fun fact: if you consider how fast electricity travels in silicium, it turns out that for a clock that pulses in the tens of billions of times per second (which is what gigahertz are), it is physically impossible for each pulse to get all the way across a 2cm die before the next pulse starts. This is exacerbated by the fact that a processor has many meandering paths throughout and is not a straight line.
So at any given moment, there are several clock cycles traveling throughout a modern processor at the same time, and the designers have to just “come up” with a solution that makes that work, nevermind the fact that almost all the digital logic design tools are not built to account for this, so instead they end up having to use analog (as in audio chips, not as in pen-and-paper design) design tools.
Signals don’t have to make it across the whole die each clock pulse. They just have to make it to the next register in their pipeline/data path, and timing tools for that absolutely exist. They treat it as analog because the signals themselves are analog and chips must account for things like the time it takes for a signal to go from a 0 to a 1 (or vice versa), as well as the time it takes to “charge” a flip flop so that it registers the signal change and holds it stable for the next stage of the pipeline.
As far as I know, clock speed is still pretty nice to have, but chip development has shifted towards adding multiple cores because it basically became technologically impossible to continue increasing clock speeds.
A nice fun fact: if you consider how fast electricity travels in silicium, it turns out that for a clock that pulses in the tens of billions of times per second (which is what gigahertz are), it is physically impossible for each pulse to get all the way across a 2cm die before the next pulse starts. This is exacerbated by the fact that a processor has many meandering paths throughout and is not a straight line.
So at any given moment, there are several clock cycles traveling throughout a modern processor at the same time, and the designers have to just “come up” with a solution that makes that work, nevermind the fact that almost all the digital logic design tools are not built to account for this, so instead they end up having to use analog (as in audio chips, not as in pen-and-paper design) design tools.
Signals don’t have to make it across the whole die each clock pulse. They just have to make it to the next register in their pipeline/data path, and timing tools for that absolutely exist. They treat it as analog because the signals themselves are analog and chips must account for things like the time it takes for a signal to go from a 0 to a 1 (or vice versa), as well as the time it takes to “charge” a flip flop so that it registers the signal change and holds it stable for the next stage of the pipeline.