It’s open source nature protects against that. People mistake Linus as being in the same boat as Stallman but Linus was only open source by circumstance, he kind infamously doesn’t seem to appreciate the role open source played in his own success.
It already directly addresses the mistakes of x86 and ARM. I don’t know what he is so worried about.
Just a reminder the RISC-V architecture is not open source as many think it is only the instruction set is open source. We remain far from a truly open/libre hardware for now
There’s plenty of designs out there that you can load onto an FPGA or, funds permitting, send off to a fab to burn into silicon.
RISC-V is the only shot we have at usable open source hardware. I really, really hope it takes off.
Whilst some open source implementations exist, RISC-V is not open source. It’s an open standard. i.e. there’s no license fee to implement it.
I didn’t know that I thought all RISC-V was open source :( I’m not as familiar with it as I’d like to be. I might just have to dive into it more and change that soon
Even if that happens, still open sauce
Not really? I mean, only partially.
He’s being misquoted by the headline. He FEARS that it will make the same mistakes. Let’s be clear about RISC is here in the first place: an open-source hardware architecture. Anyone with enough money and willpower to fork it for their needs will do so. It’s anyone’s game still. He’s just simply saying that the same type of people who took over ARM and x86 are doomed to make the same mistakes. Not that RISC-V is bad.
I’m being pedantic here but RISC-V is not a hardware architecture as in something that you can send to a manufacturer and get it made. It is an ISA. How you implement those ISA is up to you. Yes there are open implementations but I think it is important to distinguish it.
isnt ARM the same?
So does x86. The difference is license. Just like how Intel and AMD have a VERY different design (implementation) as of now, so does RISC-V. Any vendor can implement it however they want, but they won’t have to pay anyone for using RISC-V ISA
Well regardless, the world needs alternatives that are outside of restrictive US patent law and large monopolistic control. Thank god for pioneers:)
ARM Inc is an English company owned by a Japanese company
Pretty sure it’s a plc, not and Inc.
Anyone willing to summarize those mistakes here, for those who can’t watch the video rn?
Basically, his concern is that if they are not cooperating with software engineers that the product won’t be able to run AAA games.
It’s more of a warning than a prediction.
What are “AAA turns”?
Sorry, AAA games. I was swiping on my keyboard and didn’t see the mistake.
SwiftKey?
Instruction creep maybe? Pretty sure I’ve also seen stuff that seems to show that Torvalds is anti-speculative-execution due to its vulnurabilities, so he could also be referring to that.
Counterintuitive but more instructions are usually better. It enables you (but let’s be honest the compiler) to be much more specific which usually have positive performance implications for minimal if any binary size. Take for example SIMD which is hyper specific math operations on large chunks of data. These instructions are extremely specific but when properly utilized have huge performance improvements.
I understand some instruction expansions today are used to good effect in x86, but that there are also a sizeable number of instructions that are rarely utilized by compilers and are mostly only continuing to exist for backwards compatibility. That does not really make me think “more instructions are usually better”. It makes me think “CISC ISAs are usually bloated with unused instructions”.
My whole understanding is that while more specific instruction options do provide benefits, the use-cases of these instructions make up a small amount of code and often sacrifice single-cycle completion. The most commonly cited benefit for RISC is that RISC can complete more work (measured in ‘clockcycles per program’ over ‘clockrate’) in a shorter cyclecount, and it’s often argued that it does so at a lower energy cost.
I imagine that RISC-V will introduce other standards in the future (hopefully after it’s finalized the ones already waiting), hopefully with thoroughly thought out instructions that will actually find regular use.
I do see RISC-V proponents running simulated benchmarks showing RISC-V is more effective. I have not seen anything similar from x86 proponents, who usually either make general arguments, or worse , just point at the modern x86 chips that have decades of research, funding, and design behind them.
Overall, I see alot of doubt that ISAs even matter to performance in any significant fashion, and I believe it for performance at the GHz/s level of speed.
smells like linus thinks there is going to be an ever increasing tech debt, and honestly, i think i agree with him on that one.
RISCV is likely going to eventually overstep it’s role in someplaces, and bits and pieces of it will become archaic over time.
The gap between hardware and software level abstraction is huge, and that’s really hard to fill properly. You just need a strict design criteria to get around that one.
I’m personally excited to see where RISCV goes, but maybe what we truly need is a universal software level architecture that can be used on various different CPU architectures providing maximum flexibility.
overstep its* role in some places
username checks out
